This invention relates to digital processing apparatus, in particular to a system for computing the address of the next operand to be fetched from a data memory simultaneously with operation on the last operand fetched.
In array processing apparatus it is frequently necessary to operate on one ordered set, or array, of data by another ordered set of data repetitively, starting with a new data point in the first set on each successive operation. For example, in digital filtering of a signal represented by an array of samples of a signal waveform convolution is typically performed. A general expression representing the convolution of the signal x by the filter characteristic h is as follows:
P=number of coefficients of the filter characteristic ##EQU1## i=the number of a data point; O.ltoreq.i.ltoreq.P In this example each set of data points representing the waveform x is first multiplied by a corresponding coefficient of h and the sum of those products is added; thereafter, the coefficients are shifted by one position and this process is repeated. This multiplication and addition for each of the coefficients representing the filter characteristic is repeated until the entire data set representing the signal waveform has been convolved with all of the coefficients representing the filter characteristic. During each pass through the set of coefficients the addresses of the data and coefficients in the data memory must be computed after each successive multiplication and addition operation. After each such pass through the set of coefficients representing the filter characteristic, the system must return to a starting address pointing to the beginning of the set of coefficients in data memory and to a starting address pointing to the next data point in the set of data points representing the waveform, the original pointer having been updated by one.
One object ordinarily sought in array processing, particularly in signal processing, is to perform computation at high speed. This is especially important where real time processing is desirable. Where, as in the foregoing example, repetitive passes through sets of data points are necessary new addresses must be computed with each successive operation; that is, some mechanism must be provided for advancing the operand addresses during each pass and reinitializing the pointers at the beginning of every pass, including advancing the value to which a pointer is initialized.
In prior art microprocessor apparatus starting address computation typically requires that the starting addresses and the amount by which starting addresses are to be advanced be stored in a memory, that those values be fetched each time computation of a new starting address is needed, that is, for reinitializing the current address at the beginning of each new pass through a set of operands, and that the new starting address be computed. This process is accomplished by a series of program steps, that is, instructions. Apparatus which operate in this manner are represented, for example, by the TMS 320 microprocessor manufactured by Texas Instruments Corporation, and the F9445 microprocessor manufactured by Fairchild, Inc., and the ATMAC microprocessor manufactured by Radio Corporation of America. These program steps require overhead activity that increases the amount of time to accomplish an array processing operation.
Accordingly, it would be desirable to provide a mechanism that would keep track of starting and current addresses, compute new addresses as the array processing operation passes through the sets of data, and compute new starting addresses with each successive pass through a computation sequence simultaneously with the operation on the addressed operands so as to maximize the speed of array processing operations.